东莞到桂林多少公里:懂VHDL语言进啊!!!!!

又是你，改了一下，这个很简单的分频，只有一个输入，一个输出
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY frequency IS
PORT(frqin: IN std_logic;
frqout: OUT std_logic ;
END frequency；
ARCHITECTURE test OF frequency IS
SIGNAL n:bufferr integer rang 7 downto 0
SIGNAL s:bufferr std_logic ;
PROCESS
BEGIN
WAIT UNTIL (frqin'event and frqin='1');
IF n=7 THEN
s<=NOT s;
n<=0
ELSE
n<= n+1;
END IF
END PROCESS;
frqout<=s;
END test

你要分频的原信号是多少啊，clk是要分频的原信号
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY fenpin IS
PORT(clk:in std_logic；
reset: IN std_logic;
q: OUT std_logic ;
END fenpin；
ARCHITECTURE test OF fenpin IS
variable n: integer;
SIGNAL s: std_logic ;
PROCESS (clk)
BEGIN
if reset='1' then
n:=0;
s<='0';
if (clk'event and clk='1') then
IF n=7 THEN
n:=0;
s<='1';
else
n:=n+1;
s<='0';
end if;
end if;
end if;
END PROCESS;
q<=s;
end;

试试这个
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY frequency IS
PORT(frqin:IN std_logic;
frqout:OUT std_logic);
END frequency;
ARCHITECTURE test OF frequency IS
SIGNAL n:integer range 3 downto 0;
SIGNAL s:std_logic;
BEGIN
PROCESS
BEGIN
WAIT UNTIL(frqin'event and frqin='1');
IF n=3 THEN
s<=NOT s;
n<=0;
ELSE
n<=n+1;
END IF;
END PROCESS;
frqout<=s;
END test;