情侣俯卧撑gif:关于这个vhdl语言的问题,需要详细的解释,高分求助

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xxx1 is
port(c:in std_logic_vector(2 downto 0); --定义宽度为3的逻辑矢量
dp:out std_logic;
a1,a2,a3,a4,b1,b2,b3,b4:in std_logic_vector(3 downto 0);
d:out std_logic_vector(3 downto 0)); --定义宽度为4的逻辑矢量
end xxx1;
architecture rt1 of xxx1 is --定义结构体
begin
process(c,a1,a2,a3,a4,b1,b2,b3,b4) --一个进程
variable comb:std_logic_vector(2 downto 0); --定义该进程中的变量
begin
comb:=c; --变量的赋值
case comb is --多选一的条件赋值语句，为d赋值
when"000"=>d<=a1;
dp<='0';
when"001"=>d<=a2;
dp<='0';
when"010"=>d<=a3;
dp<='1';
when"011"=>d<=a4;
dp<='0';
when"100"=>d<=b1;
dp<='0';
when"101"=>d<=b2;
dp<='0';
when"110"=>d<=b3;
dp<='1';
when"111"=>d<=b4;
dp<='0';
when others=>null;
end case;
end process;
end rt1;
模块SE见图13-5。

图13-5 模块SE
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity se is
port(clk:in std_logic;
a:out std_logic_vector(2 downto 0));
end se;
architecture rt1 of se is --定义结构体
begin
process(clk) --一个计数进程
variable b:std_logic_vector(2 downto 0); --定义该进程中的变量
begin
if(clk'event and clk='1')then --0到7的循环加1计数
if(b="111")then
b:="000";
else
b:=b+1;
end if;
end if;
a<=b;
end process;
end rt1;
模块DI见图13-6

图13-6 模块DI
library ieee;
use ieee.std_logic_1164.all;
entity di is
port(d:in std_logic_vector(3 downto 0);
q:out std_logic_vector(6 downto 0));
end di;
architecture rt1 of di is --定义结构体
begin
process(d) --将d的十进制数值用七段码表示出来
begin
case d is --利用case语句为七段码q赋值
when"0000"=>q<="0111111";
when"0001"=>q<="0000110";
when"0010"=>q<="1011011";
when"0011"=>q<="1001111";
when"0100"=>q<="1100110";
when"0101"=>q<="1101101";
when"0110"=>q<="1111101";
when"0111"=>q<="0100111";
when"1000"=>q<="1111111";
when others=>q<="1101111";
end case;
end process;
end rt1;

你在什么地方复制来的，乱七八糟的