成都市蜀安印章qq:会VHDL的高手进来帮下忙！！！

帮我注释下下面的程序！谢谢！
1．+V码检测模块VHDL程序设计
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Entity zv is
Port(fb,zb:in std_logic;
Zvout:out std_logic);
End zv;
Architecture bh of zv is
Signal M:std_logic_vector(2 dpwnto 0);
Begin
Process(zb,fb)
Begin
If fb= ‘1’ then M <= “000”;
Elsif zb`event and zb= ‘1’ then
If M<2 then
M<=M+1;
End if;
end if;
end process;
process(Fb,M)
begin
if FB= ‘0’ then
if M<2 then
zvout<= ‘0’;
else
zvout<=zb;
end if;
else
zvout<= ‘0’;
else
zvout<=zb;
end if
else
zvout<= ‘0’;
end if;
end process;
end bh;
architecture hh of V is
signal N:std_logic_vector(2 downto 0);
begin
process(zb,fb)
begin
if zb= ‘1’then n<= “000”;
elsif fb`event and fb= ‘1’ then
if N<2 then
N<=N+1;
End if;
End if;
End process;
Process(zb,N)
Begin
If N<2 then
Fvout<=’0’
Else
Fvout<=fb;
End if;
Else
Fvout<=’0’;
End if;
End process;
End hh;
2.-V码检测模块的VHDL 程序设计
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Entity fv is
Port (fb,zb:IN STD_LOGIC;
Fvout:out std_logic);
End FV;
Architecture hh of FV is
Signal M:std_logic_vector(2 dpwnto 0);
Begin
Process(zb,fb)
Begin
If fb= ‘1’ then N <= “000”;
Elsif zb`event and fb= ‘1’ then
If N<2 then
N<=N+1;
End if;
end if;
end process;
process(ZB,N)
begin
if zb= ‘0’ then
if N<2 then
fvout<= ‘0’;
else
fvout<=fb;
end if;
else
fVOUT<= ‘0’;
end if;
end process;
end hh;
3.扣V扣B模块程序设计
Library ieee;
Use ieee.std_logic_1164.all;
Entity kvb is
Port(clk:in std_logic;
V,datain:in std_logic;
Decode:out std_logic
);
End kvb
Architecture behave of kvb is
Signal A0,A1,A2,A3:std_logic;
Begin
Process(clk,v)
Begin
If clk`event and clk= ‘1’ then
If (v= ‘1’)then
A0<= ‘0’;
A1<= ‘0’;
A2<= ‘0’;
A3<= ‘0’;
Decode <=A0;
Slsif(V= ‘0’)then
A3,=datain;
A2<=A3;
A1<=A2;
A0<=A1;
Decode <=A0;
End if
End if;
End process;
End behave;
4.加法器程序设计
Library ieee;
Use ieee.std_logic_1164.all;
Entuty orl is
Port(a,b:in std_logic;c: out std_logic);
End entity orl;
Architecture one of orl is
Begin
C<=a or b;
End architecture;